- Project status
- Project start date
- 3 Feb 2019
- Project posted
- 13 Jan 2019 13:44
- Project duration (approx.)
- 6 Months
- Budget (approx.)
- US$400 / day
- Level of Experience
- Area of expertise
- Product Development
- Consultant location
- English (Essential) , Hebrew (Essential)
Objectives and Key Deliverables
• Leading verification tasks on one of our next generation cellular distribution device.
• Creating and implementing test plans for module and system level of RTL design.
• Implementing UVM based verification components.
• Integrating verification IPs.
• Work in a matrix organization in close collaboration with all disciplines (Design, System, SW, System validation).
Education, Experience, and other Qualifications:
• B.Sc. in electrical engineering or computer science.
• 4+ years of experience in UVM methodology (System Verilog).
• High level of English.
Will be major advantage
• Experience with both Verilog & VHDL.
• Experience with Xilinx tools.
• Experience with Synopsys tools.
Will be an advantage
• Experience with svn.
• Experience with scripting language (Python, Perl, Bash).
• Experience with ARM architecture and bus protocols.
• Experience with Matlab & Simulink.
• Knowledge in analog & digital networks.
Scope: 6-12 months. Full time . No travel required